library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- use work.ALU_components_pack.all;


entity Arithmetic is
	Port(
		A_arithmetic        : in  std_logic_vector(7 downto 0);
		B_arithmetic        : in  std_logic_vector(7 downto 0);
		FN_arithmetic       : in  STD_LOGIC_VECTOR(2 downto 0);
		result_arithmetic   : out STD_LOGIC_VECTOR(7 downto 0);
		overflow_arithmetic : out STD_LOGIC;
		sign_arithmetic     : out STD_LOGIC
	);
end Arithmetic;

architecture Behavioral of Arithmetic is

-- Define signals here if needed.


begin
	process(FN_arithmetic, A_arithmetic, B_arithmetic)
		variable oA             : std_logic_vector(8 downto 0);
		variable oB             : std_logic_vector(8 downto 0);
		variable check_overflow : std_logic_vector(8 downto 0);
	--variable check_signed   : SIGNED(8 downto 0);
	--variable sA             : SIGNED(8 downto 0);
	--variable sB             : SIGNED(8 downto 0);

	-- define variables here if needed.    

	begin
		oA                  := ('0' & A_arithmetic);
		oB                  := ('0' & B_arithmetic);
		--sA                  := to_signed(A_arithmetic,7);
		--sB                  := ('0' & A_arithmetic);
		overflow_arithmetic <= '0';
		sign_arithmetic     <= '0';
		-- develope the behavioral code here.
		case FN_arithmetic is
			when "000" =>
				result_arithmetic <= A_arithmetic;

			when "001" =>
				result_arithmetic <= B_arithmetic;

			when "010" =>
				check_overflow    := oA + oB;
				result_arithmetic <= A_arithmetic + B_arithmetic;
				if (check_overflow(8) = '1') then
					overflow_arithmetic <= '1';
				end if;

			when "011" =>
				if (B_arithmetic > A_arithmetic) then
					sign_arithmetic <= '1';

				end if;
				result_arithmetic <= A_arithmetic - B_arithmetic;
			when others =>
		end case;

	end process;
end Behavioral;
